The present invention relates to a large scale integrated semiconductor device (LSI), and more specifically relates to a gate array having a delay circuit and/or a pull-up or pull-down circuit.
Keeping pace with the increase in the integration density of semiconductor devices, circuits included in LSI have become more complicated. The gate array is a technology for facilitating the manufacture of a custom-tailored LSI in a short turnaround time and at a low cost.
An LSI having a gate array structure mainly comprises two kinds of components, namely basic cells and input/output (I/O) cells. The basic cell is for forming a circuit provided with logic functions required for the LSI, while the I/O cell is for forming a circuit responsible for the logic level conversion between the circuits in the LSI and the circuits outside the LSI. The basic cell is formed at the inner area of a semiconductor substrate, while the I/O cell is formed outside the periphery of the area containing the basic cells. An exemplary configuration of such LSI is disclosed in the U. S. Pat. No. 4,412,237, issued Oct. 25, 1983.
FIG. 1 (a) is a plan view of an exemplary pattern of the basic cell in a conventional gate array, and FIG. 1(b) is an equivalent circuit diagram of the basic cell shown in FIG. 1 (a), wherein like reference characters designate corresponding parts.
Referring to FIGS. 1(a) and 1(b), the basic cell includes two pairs of transistors each comprising a p-channel transistor and a n-channel transistor. namely, the first pair comprises the p-channel transistor P.sub.1 and the n-channel transistor N.sub.1, and the second pair comprises the p-channel transistor P.sub.2 and the n-channel transistor N.sub.2. In each of the pairs, the gates of the p-channel and n-channel transistors are commonly connected to each other to form a single common gate. That is, the electrodes GA and GB, on opposite sides of the p-channel transistor region 100 and the n-channel transistor region 200, form the common gate for the p-channel transistor P.sub.1 and the n-channel transistor N.sub.1 and the common gate for the p-channel transistor P.sub.2 and the n-channel transistor N.sub.2, respectively. Each of the p-channel and n-channel transistors has a specified transconductance (gm), which depends on the gate width W and gate length L.
The p-channel transistors P.sub.1 and P.sub.2 are connected to each other by a p-type impurity diffusion region 1 which forms the common source or drain of these p-channel transistors, and the n-channel transistors N.sub.1 and N.sub.2 are connected to each other by a n-type impurity diffusion region 5 which forms the common source or drain of these n-channel transistors. The p-type impurity diffusion regions 2 and 3 respectively, form the sources or drains of the p-channel transistors P.sub.1 and P.sub.2, while the n-type impurity diffusion regions 4 and 6 respectively form the sources or drains of the n-channel transistors N.sub.1 and N.sub.2.
A number of the basic cells shown in FIGS. 1(a) and 1(b), are arranged on a semiconductor substrate so as to form a plurality of arrays, and are interconnected by wiring lines distributed in spaces (each referred to as a wiring region) between the adjacent arrays, hence an LSI device having desired logic functions is provided.
In an LSI semiconductor device, a delay circuit is needed for adjusting the timing of the signals transmitted through the component circuit blocks forming the LSI network. However, in a masterslice semiconductor device such as a gate array, it is difficult to obtain the relatively large time constant necessary for obtaining a sufficient delay. This is mainly because the resistive components available in a masterslice are transistors and resistors which have relatively high gms.
A means employed for obtaining the necessary delay in a masterslice semiconductor device is a circuit comprising multiple-staged inverter circuit (20 stages of inverters, for instance). However, because of the high gms of transistors constituting each of the inverters, this delay circuit consumes 20 basic cells each as shown in FIGS. 1(a) and 1(b) in order to obtain a delay of few tens of a nanosecond.
Another means for obtaining delay is to use the resistance and parasitic capacity of the aluminum wiring line interconnecting circuit blocks between which a specified amount of delay is required. To obtain the resistance necessary for attaining the delay in this method, the aluminum wiring line must be so long that it is capable of interconnecting two basic cells separated by tens or hundreds of basic cells therebetween. Therefore, the circuit blocks are usually formed from basic cells remote from each other, as a result, the layout of the circuit blocks is severely restricted.
Another means which is disclosed in Japanese application (Tokkaisho No. 57-133712, issued Aug. 18, 1982) is to utilize the resistivity of a polysilicon gate electrode of a transistor in the basic cell. That is, an interconnection on which a specified delay is required is performed via a necessary number of polysilicon gate electrodes connected in series, hence the delay, determined by the resistance and the parasitic capacity of the polysilicon gate electrodes, is provided. In this method, the delay is attained at the sacrifice of a number of basic cells, for example, ten basic cells, each including four transistors are made ineffective for obtaining a delay of few tens of a nanosecond.
Further, a pull-up or pull-down circuit is needed for the input/output interface circuit of a CMOS (Completmentary Metal Oxide Semiconductor) LSI device, when the LSI device is connected to an external circuit such as a tri-state buffer whose output occasionally takes a high impedance state. As the pull-up or pull-down circuit, a resistor of a few tens of a kilo-ohm is necessary. However in the prior art gate array, it is difficult to form such a pull-up or pull-down circuit by using the basic cell, because the transistors in the basic cell have excessively high gms for this purpose. Even if the polysilicon gate electrodes are used as the resistor, basic cells, as many as ten times those used for forming the above described delay circuit, are necessary. Thus, an external resistor has been necessary in a conventional gate array requiring a pull-up or pull-down circuit.